1. Technical Field
This disclosure relates to integrated circuit design, and more particularly to estimating power in an integrated circuit design.
2. Description of the Related Art
Integrated circuit design flow is a complex process. An important part of the design process is the simulation performed on models of the integrated circuit at various levels of the design hierarchy, for example at system level, logic level, and/or circuit level. The circuit models are oftentimes created with use of a hardware description language (HDL) such as Verilog or VHDL (Very high level integrated circuits Hardware Description Language). Generally, a synthesis program is used to generate a netlist from the HDL models, making use of standard cell libraries containing a variety of circuit elements from which the integrated circuit may be constructed. Netlists usually include instances of the standard cells contained in the design, with the possible inclusion of custom blocks, and information descriptive of the connectivity between all the instances included in the integrated circuit. There are different types of netlists that can be used, including physical and logical netlists, instance-based and net-based netlists, and flat and hierarchical netlists. In many cases circuit power estimation is critical. This is particularly true in the case of circuits intended for mobile applications. Various simulations may be performed on circuit models of circuits to be fabricated for use in mobile applications.
In many cases, SPICE (Simulation Program with Integrated Circuit Emphasis) simulations are performed to generate and cull at least a portion of the information pertaining to projected power consumption of the integrated circuit/system. Running SPICE simulations can be error prone, however, when manually placing monitor statements into the netlist at different levels of hierarchy. In addition, providing fine-grained power measurement is typically difficult to achieve when instrumenting the SPICE circuit model using, for example, monitor statements.